module prbs_checker (
    input wire clk,
    input wire rst,
    input wire enable,
    input wire prbs_bit,
    output reg done,
    output reg detected
);
    reg [7:0] lfsr;
    reg [7:0] counter;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            lfsr <= 8'h1; // 初值需与 generator 相同
            counter <= 0;
            done <= 0;
            detected <= 0;
        end else if (enable && !done) begin
            // Feedback = MSB XOR taps XOR 输入 bit
            wire feedback = lfsr[7] ^ lfsr[5] ^ lfsr[4] ^ lfsr[3] ^ prbs_bit;
            lfsr <= {lfsr[6:0], feedback};

            counter <= counter + 1;

            if (counter == 8'd254) begin  // N=8, 周期 = 2^8 - 1 = 255
                done <= 1;
                if (lfsr == 8'b0)
                    detected <= 1;  // 检测成功
                else
                    detected <= 0;  // 检测失败
            end
        end
    end

endmodule
